Accompanied with the prospering semiconductor and electronic information industries, various integrated circuit components are extensively applied in all sorts of application fields including communication, signal processing, and algorithmic estimation. In a current deep sub-micron manufacturing process, a high performance integrated circuit performs algorithms with an overwhelmingly fast speed, and carries out signal exchange and communication with other components via an I/O interface.
FIG. 1 shows a schematic diagram of an I/O interface of an integrated circuit in the prior art. An I/O interface 10 comprises a plurality of I/O pins 100, each of which has a clock trigger input 1000. The I/O pin 100 receives or transmits data signals according to a received clock trigger.
In practice, the I/O pin 100 of the I/O interface 10 adopts different clocks according to the nature of signals and the recipient of signal transmission. As shown in FIG. 1, there are a first clock signal Clk, a second clock signal Clk2, and a third clock signal Clk3. The I/O pins responding to the Clk are marked as Data; the I/O pins responding to the clock signal Clk2 are marked as Data2; and the I/O pins responding the clock signal Clk3 are marked as Data3. More specifically, the clock signal Clk, Clk2, or Clk3 needs to be electrically connected to the clock trigger input of the I/O pin 100 marked as Data, Data2, or Data3 to drive and control signal reception and transmission at the particular I/O pin 100.
FIG. 2 shows a schematic diagram illustrating a relationship between the clock signal Clk and the I/O interface 10. As shown, the clock signal Clk is connected through a plurality of independent wires to each of the I/O pins 100 (marked as Data) that need the clock signal Clk. Such clock distributing method is indeed rather simple, however, as observed from FIG. 2, lengths of the wires between I/O pins and the clock input are quite different, which means that certain clock differences may exist between the I/O pins to lead to an issue that data signals are not received and transmitted in synchronization. Further, on top of putting a burden on the space required for laying out the wires, the great amount of independent wires also increases manufacturing cost.
Therefore, an available common solution for overcoming the above drawbacks is providing a clock tree that corresponds to the I/O interface, and clock triggers are then respectively transmitted to the I/O pins of the I/O interface via the clock tree. In the design of the clock tree, load balance, time deviation, routing rules and wire characteristics (e.g., wire lengths, driving capabilities and slew rate) are taken into consideration. In addition, an I/O interface is generally a two-dimensional structure such as the U-shape shown in FIG. 1 but not a simple linear arrangement, so that the design of a corresponding clock tree becomes even more difficult.
In some existing high-speed I/O interfaces such as SSTL2 (i.e., DDR2), SSTL3 (i.e., DDR3), Serial Advanced Technology Attachment (SATA) and Peripheral Component Interconnect Express (PCIe), transmission rate unceasingly increases such that standards for clock signals are also continuously raised.
To solve the abovementioned drawbacks, according to the invention, a clock tree distributing method for establishing a clock tree is provided, wherein the established clock tree is capable of achieving clock balance of a high-speed I/O interface.